The present invention relates to the field of network communications, and more particularly, to the testing of a memory arrangement of a network interface controller.
Network interface controllers handle the transmission and reception of frame data between a transmitting network station and a receiving network station via a network communications system, such as a local area network. For transmission, frame data is sent from an upper layer down through a driver layer, a media access controller layer and then to a physical layer. In the transmitting network station, a central processor unit writes frame data and associated descriptors into system memory where a network interface controller reads the frame data and transmits the frame data onto the network. At the receiving network station a network interface controller stores the frame data into memory.
Clock speed and data transfer rates differ between the network and system sides of the network interface controller. Therefore, it is necessary to incorporate some quantity of data storage within the network interface controller. In some applications, it is advantageous for the network interface controller to incorporate a large amount of storage. The desired memory size may exceed that which can practically be integrated in a single-chip design, requiring external memory and an associated interface. This external memory, along with the PC board traces and connections, as well as parts of the logic within the network controller, comprise a memory subsystem. Failures in the memory subsystem may result from electrical or mechanical failure of any of the elements of the system and/or errors in the design of the PC board such as excessive loading or trace length.
In conventional MBIST logic, the test information, including any failing information, is read out of the text logic in a serial fashion via a test interface. This is appropriate for component test, as it minimizes the number of package pins needed for the test interface. It is, however, inappropriate for MBIST tests run during system test. At this time, the test interface is typically not accessible and serial access is burdensome for the central processor, as each bit requires a separate transaction to read.
There is a need for a method and arrangement for performing an MBIST that allows a processor or other component more flexibility in reading failing information from an MBIST.
This and other needs are met by the present invention which provides a network interface controller comprising a testable memory arrangement, a computer bus interface for coupling the network interface controller to an external central processing unit (CPU), a memory built-in self test (MBIST) controller configured to test the memory arrangement with an MBIST and generate MBIST results, and a register coupled to the MBIST controller and the computer bus interface. The register is configured to receive and store the MBIST results, and to be readable by a CPU through the computer bus interface.
The use of a register that can be read out through a computer bus interface allows the failing information to be read in a manner more convenient for a processor coupled to the network controller interface. Instead of being shifted out serially, through a shift register and requiring immediate attention, the storage of the failing information in readable registers allows a processor to read that information (in a PCI read, for example) at a time determined by the processor.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of testing a memory arrangement of a network interface controller. This method comprises the steps of conducting a memory built-in self test (MBIST) on the memory arrangement, storing failing information of the MBIST in a register in the network interface controller, and reading the failing information in the register by a component external to the network interface controller.